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3 v/5 v, 2 msps, 8-bit, 1-/4-/8-channel sampling adcs ad7822/ad7825/ad7829 rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features 8-bit half-flash adc with 420 ns conversion time one, four, and eight single-ended analog input channels available with input offset adjust on-chip track-and-hold snr performance given for input frequencies up to 10 mhz on-chip reference (2.5 v) automatic power-down at the end of conversion wide operating supply range 3 v 10% and 5 v 10% input ranges 0 v to 2 v p-p, v dd = 3 v 10% 0 v to 2.5 v p-p, v dd = 5 v 10% flexible parallel interface with eoc pulse to allow standalone operation applications data acquisition systems, dsp front ends disk drives mobile communication systems, subsampling applications general description the ad7822/ad7825/ad7829 are high speed, 1-, 4-, and 8-channel, microprocessor-compatible, 8-bit analog-to-digital converters with a maximum throughput of 2 msps. the ad7822/ ad7825/ad7829 contain an on-chip reference of 2.5 v (2% tolerance); a track-and-hold amplifier; a 420 ns, 8-bit half- flash adc; and a high speed parallel interface. the converters can operate from a single 3 v 10% and 5 v 10% supply. the ad7822/ad7825/ad7829 combine the convert start and power-down functions at one pin, that is, the convst pin. this allows a unique automatic power-down at the end of a conversion to be implemented. the logic level on the convst pin is sampled after the end of a conversion when an eoc (end of conversion) signal goes high. if it is logic low at that point, the adc is powered down. the ad7822 and ad7825 also have a separate power-down pin (see the operating modes section). the parallel interface is designed to allow easy interfacing to microprocessors and dsps. using only address decoding logic, the parts are easily mapped into the microprocessor address space. the eoc pulse allows the adcs to be used in a stand- alone manner (see the parallel interface section.) functional block diagram convst parallel port v ref in/out eoc rd cs agnd v mid a0 1 a1 1 a2 2 v in1 v in2 4 v in3 4 v in4 4 v in5 5 v in6 5 v in7 5 v in8 5 comp pd 3 2.5v ref v dd control logic dgnd input mux t/h buf db0 db7 1 a0, a1 ad7825/ad7829 2 a2 ad7829 3 pd ad7822/ad7825 4 v in2 to v in4 ad7825/ad7829 5 v in5 to v in8 ad7829 8-bit half flash adc 01321-001 figure 1. the ad7822 and ad7825 are available in 20-lead and 24-lead, 0.3" wide, plastic dual in-line packages (pdip); 20-lead and 24-lead standard small outline packages (soic); and 20-lead and 24-lead thin shrink small outline packages (tssop). the ad7829 is available in a 28-lead, 0.6" wide pdip; a 28-lead soic; and a 28-lead tssop. product highlights 1. fast conversion time. the ad7822/ad7825/ad7829 have a conversion time of 420 ns. faster conversion times maximize the dsp processing time in a real-time system. 2. analog input span adjustment. the v mid pin allows the user to offset the input span. this feature can reduce the requirements of single-supply op amps and take into account any system offsets. 3. fpbw (full power bandwidth) of track-and-hold. the track-and-hold amplifier has an excellent high frequency performance. the ad7822/ad7825/ad7829 are capable of converting full-scale input signals up to a frequency of 10 mhz. this makes the parts ideally suited to subsampling applications. 4. channel selection. channel selection is made without the necessity of writing to the part.
ad7822/ad7825/ad7829 rev. c | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 product highlights ....................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing characteristics ................................................................ 5 timing diagram ........................................................................... 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configurations and function descriptions ........................... 7 ter mi nolo g y ...................................................................................... 8 circuit information ........................................................................ 10 circuit description ..................................................................... 10 typical connection diagram ................................................... 10 adc transfer function ............................................................. 11 analog input ............................................................................... 11 power-up times ......................................................................... 14 power vs. throughput ................................................................ 15 operating modes ........................................................................ 15 parallel interface ......................................................................... 17 microprocessor interfacing ........................................................... 18 ad7822/ad7825/ad7829 to 8051 ......................................... 18 ad7822/ad7825/ad7829 to pic16c6x/pic16c7x ................ 18 ad7822/ad7825/ad7829 to adsp-21xx ............................. 18 interfacing multiplexer address inputs .................................. 18 ad7822 standalone operation ................................................ 19 outline dimensions ....................................................................... 20 ordering guide .......................................................................... 25 revision history 8/06rev. b to rev. c changes to general description .................................................... 1 changes to table 1............................................................................ 3 changes to typical connection diagram section ..................... 10 updated outline dimensions ....................................................... 20 changes to ordering guide .......................................................... 25 10/01rev. a to rev. b changes to power requirements.................................................... 3 changes to pin function description ........................................... 5 changes to circuit description ...................................................... 7 changes to typical connection diagram section........................7 changes to analog input section....................................................8 changes to analog input selection section...................................9 changes to power-up times section .......................................... 10 changes to power vs. throughput section ................................. 11 added ad7822 stand-alone operation section ....................... 15 12/99 rev. 0 to rev. a
ad7822/ad7825/ad7829 rev. c | page 3 of 28 specifications v dd = 3 v 10%, v dd = 5 v 10%, gnd = 0 v, v ref in/out = 2.5 v. all specifications ?40c to +85c, unless otherwise noted. table 1. parameter version b unit test condition/comment dynamic performance f in = 30 khz, f sample = 2 mhz signal to (noise + distortion) ratio 1 48 db min total harmonic distortion 1 ?55 db max peak harmonic or spurious noise 1 ?55 db max intermodulation distortion 1 fa = 27.3 khz, fb = 28.3 khz second-order terms ?65 db typ third-order terms ?65 db typ channel-to-channel isolation 1 ?70 db typ f in = 20 khz dc accuracy resolution 8 bits minimum resolution for which no missing codes are guaranteed 8 bits integral nonlinearity (inl) 1 0.75 lsb max differential nonlinearity (dnl) 1 0.75 lsb max gain error 1 2 lsb max gain error match 1 0.1 lsb typ offset error 1 1 lsb max offset error match 1 0.1 lsb typ analog inputs 2 see analog input section v dd = 5 v 10% input voltage span = 2.5 v v in1 to v in8 input voltage v dd v max 0 v min v mid input voltage v dd ? 1.25 v max default v mid = 1.25 v 1.25 v min v dd = 3 v 10% input voltage span = 2 v v in1 to v in8 input voltage v dd v max 0 v min v mid input voltage v dd ? 1 v max default v mid = 1 v 1 v min v in input leakage current 1 a max v in input capacitance 15 pf max v mid input impedance 6 k typ reference input v ref in/out input voltage range 2.55 v max 2.5 v + 2% 2.45 v min 2.5 v ? 2% input current 1 a typ 100 a max on-chip reference nominal 2.5 v reference error 50 mv max temperature coefficient 50 ppm/c typ logic inputs input high voltage, v inh 2.4 v min v dd = 5 v 10% input low voltage, v inl 0.8 v max v dd = 5 v 10% input high voltage, v inh 2 v min v dd = 3 v 10% input low voltage, v inl 0.4 v max v dd = 3 v 10% input current, i in 1 a max 10 na typical, v in = 0 v to v dd input capacitance, c in 10 pf max
ad7822/ad7825/ad7829 rev. c | page 4 of 28 parameter version b unit test condition/comment logic outputs output high voltage, v oh i source = 200 a 4 v min v dd = 5 v 10% 2.4 v min v dd = 3 v 10% output low voltage, v ol i sink = 200 a 0.4 v max v dd = 5 v 10% 0.2 v max v dd = 3 v 10% high impedance leakage current 1 a max high impedance capacitance 10 pf max conversion rate track-and-hold acquisition time 200 ns max see circuit description section conversion time 420 ns max power supply rejection v dd 10% 1 lsb max power requirements v dd 4.5 v min 5 v 10%; for specified performance 5.5 v max v dd 2.7 v min 3 v 10%; for specified performance 3.3 v max i dd normal operation 12 ma max 8 ma typical power-down 5 a max logic inputs = 0 v or v dd 0.2 a typ power dissipation v dd = 3 v normal operation 36 mw max 24 mw typical power-down 200 ksps 9.58 mw typ 500 ksps 23.94 mw typ 1 see the terminology section of this data sheet. 2 refer to the analog input section for an ex planation of the analog input(s).
ad7822/ad7825/ad7829 rev. c | page 5 of 28 timing characteristics v ref in/out = 2.5 v. all specifications ?40c to +85c, unless otherwise noted. table 2. parameter 1 , 2 5 v 10% 3 v 10% unit conditions/comments t 1 420 420 ns max conversion time t 2 20 20 ns min minimum convst pulse width t 3 30 30 ns min minimum time between the rising edge of rd and the next falling edge of convert star t 4 110 110 ns max eoc pulse width 70 70 ns min t 5 10 10 ns max rd rising edge to eoc pulse high t 6 0 0 ns min cs to rd setup time t 7 0 0 ns min cs to rd hold time t 8 30 30 ns min minimum rd pulse width t 9 3 10 20 ns max data access time after rd low t 10 4 5 5 ns min bus relinquish time after rd high 20 20 ns max t 11 10 10 ns min address setup time before falling edge of rd t 12 15 15 ns min address hold time after falling edge of rd t 13 200 200 ns min minimum time between new channel selection and convert start t power up 25 25 s typ power-up time from rising edge of convst using on-chip reference t power up 1 1 s max power-up time from rising edge of convst using external 2.5 v reference 1 sample tested to ensure compliance. 2 see figure 24, figure 25, and figure 26. 3 measured with the load circuit of figure 2 and defined as the time required for an output to cross 0.8 v or 2.4 v with v dd = 5 v 10%, and time required for an output to cross 0.4 v or 2.0 v with v dd = 3 v 10%. 4 derived from the measured time taken by the data outputs to change 0.5 v when loaded with the circuit of figure 2. the measure d number is then extrapolated back to remove the effects of charging or discharging the 50 pf capacitor. this means that the time, t 10 , quoted in the timing characteristic s is the true bus relinquish time of the part and, as such, is independent of external bus loading capacitances. timing diagram 200a i ol 200a i oh 2.1v to output pin c l 50pf 01321-002 figure 2. load circuit for access time and bus relinquish time
ad7822/ad7825/ad7829 rev. c | page 6 of 28 absolute maximum ratings t a = 25c, unless otherwise noted. table 3. parameter rating v dd to agnd ?0.3 v to +7 v v dd to dgnd ?0.3 v to +7 v analog input voltage to agnd v in1 to v in8 ?0.3 v to v dd + 0.3 v reference input voltage to agnd ?0.3 v to v dd + 0.3 v v mid input voltage to agnd ?0.3 v to v dd + 0.3 v digital input voltage to dgnd ?0.3 v to v dd + 0.3 v digital output voltage to dgnd ?0.3 v to v dd + 0.3 v operating temperature range industrial (b version) ?40c to +85c storage temperature range ?65c to +150c junction temperature 150c pdip package, power dissipation 450 mw ja thermal impedance 105c/w lead temperature, (soldering, 10 sec) 260c soic package, power dissipation 450 mw ja thermal impedance 75c/w lead temperature, soldering vapor phase (60 sec) 215c infrared (15 sec) 220c tssop package, power dissipation 450 mw ja thermal impedance 128c/w lead temperature, soldering vapor phase (60 sec) 215c infrared (15 sec) 220c esd 1 kv stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad7822/ad7825/ad7829 rev. c | page 7 of 28 pin configurations and function descriptions db2 1 db1 2 db0 3 convst 4 db3 20 db4 19 db5 18 db6 17 cs 5 rd 6 dgnd 7 db7 16 agnd 15 v dd 14 eoc 8 v ref in/out 13 pd 9 v mid 12 nc 10 v in1 11 nc = no connect ad7822 top view (not to scale) 01321-003 db2 1 db1 2 db0 3 convst 4 db3 24 db4 23 db5 22 db6 21 cs 5 db7 20 rd 6 agnd 19 dgnd 7 v dd 18 eoc 8 v ref in/out 17 a1 9 v mid 16 a0 10 v in1 15 pd 11 v in2 14 v in4 12 v in3 13 ad7825 top view (not to scale) 0 1321-004 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 db1 db0 convst dgnd rd cs db2 db4 db5 db6 v dd agnd db7 eoc a2 a1 v in6 v in8 a0 v ref in/out v mid v in1 v in5 v in7 v in4 v in3 v in2 db3 ad7829 top view (not to scale) 01321-005 figure 3. pin configuration figure 4. pin configuration figure 5. pin configuration table 4. pin function descriptions mnemonic description v in1 to v in8 analog input channels. the ad7822 has a single input channe l; the ad7825 and ad7829 have four and eight analog input channels, respectively. the inputs have an input span of 2.5 v and 2 v depending on the supply voltage (v dd ). this span can be centered anywhere in the range agnd to v dd using the v mid pin. the default input range (v mid unconnected) is agnd to 2 v (v dd = 3 v 10%) or agnd to 2.5 v (v dd = 5 v 10%). see the analog input section of the data sheet for more information. v dd positive supply voltage, 3 v 10% and 5 v 10%. agnd analog ground. ground reference for track-and-hold, comparators, reference circuit, and multiplexer. dgnd digital ground. ground reference for digital circuitry. convst logic input signal. the convert start signal initiates an 8-bit analog-to-digital conversion on the falling edge of this signa l. the falling edge of this signal places the track-and-hold in hold mode. the track-and-hold goes into track mode again 120 ns after the start of a conversion. the state of the convst signal is checked at the end of a conversion. if it is logic low, the ad7822/ ad7825/ad7829 powers down (see the operating modes section of the data sheet). eoc logic output. the end-of-conversion signal indicates when a conversion has finished. the signal can be used to interrupt a microcontroller when a conversion has finished or latch data into a gate array (see the parallel interface section). cs logic input signal. the chip select signal is used to enab le the parallel port of the ad7822/ ad7825/ad7829. this is necessary if the adc is sharing a common data bus with another device. pd logic input. the power-down pin is present on the ad7822 and ad7825 only. bringing the pd pin low places the ad7822 and ad7825 in power-down mode. the adcs power up when pd is brought logic high again. rd logic input signal. the read signal is used to take the outp ut buffers out of their high impedance state and drive data onto the data bus. the signal is internally gated with the cs signal. both rd and cs must be logic low to enable the data bus. a0 to a2 channel address inputs. the address of the next multiplexe r channel must be present on these inputs when the rd signal goes low. db0 to db7 data output lines. they are normally held in a high impedan ce state. data is driven onto the data bus when both rd and cs go active low. v ref in/out analog input and output. an external reference can be co nnected to the ad7822/ad7825/ad7829 at this pin. the on-chip reference is also available at this pin. when using the internal reference, this pin can be left unconnected or, in some cases, it can be decoupled to agnd with a 0.1 f capacitor. v mid the v mid pin, if connected, is used to center the analog input span anywhere in the range of agnd to v dd (see the analog input section).
ad7822/ad7825/ad7829 rev. c | page 8 of 28 terminology signal-to-(noise + distortion) ratio the measured ratio of signal-to-(noise + distortion) at the output of the analog-to-digital converter. the signal is the rms amplitude of the fundamental. noise is the rms sum of all nonfundamental signals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent upon the number of quantization levels in the digitization process: the more levels, the smaller the quantization noise. the theoretical signal-to-(noise + distortion) ratio for an ideal n-bit converter with a sine wave input is given by signal-to- ( noise + distortion ) = (6.02 n + 1.76) db thus, for an 8-bit converter, this is 50 db. total harmonic distortion (thd) the ratio of the rms sum of harmonics to the fundamental. for the ad7822/ad7825/ad7829, it is defined as 1 65 32 v vvvvv thd 222 4 22 log20(db) ++++ = where v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second through the sixth harmonics. peak harmonic or spurious noise the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2 and excluding dc) to the rms value of the fundamental. normally, the value of this specification is determined by the largest harmonic in the spectrum, but for parts where the harmonics are buried in the noise floor, it is a noise peak. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa nfb, where m, n = 0, 1, 2, 3, . intermodulation terms are those for which neither m nor n is equal to zero. for example, the second-order terms include (fa + fb) and (fa ? fb), and the third-order terms include (2fa + fb), (2fa ? fb), (fa + 2fb), and (fa ? 2fb). the ad7822/ad7825/ad7829 are tested using the ccif standard, where two input frequencies near the top end of the input bandwidth are used. in this case, the second- and third- order terms are of different significance. the second-order terms are usually distanced in frequency from the original sine waves, and the third-order terms are usually at a frequency close to the input frequencies. as a result, the second- and third-order terms are specified separately. the calculation of the intermodulation distortion is as per the thd specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental expressed in decibels (db). channel-to-channel isolation a measure of the level of crosstalk between channels. it is measured by applying a full-scale 20 khz sine wave signal to one input channel and determining how much that signal is attenuated in each of the other channels. the figure given is the worst case across all four or eight channels of the ad7825 and ad7829, respectively. relative accuracy or endpoint nonlinearity the maximum deviation from a straight line passing through the endpoints of the adc transfer function. differential nonlinearity the difference between the measured and the ideal one lsb change between any two adjacent codes in the adc. offset error the deviation of the 128th code transition (01111111) to (10000000) from the ideal, that is, v mid . offset error match the difference in offset error between any two channels. zero-scale error the deviation of the first code transition (00000000) to (00000001) from the ideal; that is, v mid ? 1.25 v + 1 lsb (v dd = 5 v 10%), or v mid ? 1.0 v + 1 lsb (v dd = 3 v 10%). full-scale error the deviation of the last code transition (11111110) to (11111111) from the ideal; that is, v mid + 1.25 v ? 1 lsb (v dd = 5 v 10%), or v mid + 1.0 v ? 1 lsb (v dd = 3 v 10%).
ad7822/ad7825/ad7829 rev. c | page 9 of 28 gain error the deviation of the last code transition (1111 . . . 110) to (1111 . . . 111) from the ideal, that is, v ref ? 1 lsb, after the offset error has been adjusted out. gain error match the difference in gain error between any two channels. track-and-hold acquisition time the time required for the output of the track-and-hold amplifier to reach its final value, within 1/2 lsb, after the point at which the track-and-hold returns to track mode. this happens approximately 120 ns after the falling edge of convst . it also applies to situations where a change in the selected input channel takes place or where there is a step input change on the input voltage applied to the selected v in input of the ad7822/ ad7825/ad7829. it means that the user must wait for the duration of the track-and-hold acquisition time after a channel change/step input change to v in before starting another conversion, to ensure that the part operates to specification. psr (power supply rejection) variations in power supply affect the full-scale transition but not the converter linearity. power supply rejection is the maximum change in the full-scale transition point due to a change in power supply voltage from the nominal value.
ad7822/ad7825/ad7829 rev. c | page 10 of 28 circuit information circuit description the ad7822/ad7825/ad7829 consist of a track-and-hold amplifier followed by a half-flash analog-to-digital converter. these devices use a half-flash conversion technique where one 4-bit flash adc is used to achieve an 8-bit result. the 4-bit flash adc contains a sampling capacitor followed by 15 comparators that compare the unknown input to a reference ladder to achieve a 4-bit result. this first flash (that is, coarse conversion) provides the four msbs. for a full 8-bit reading to be realized, a second flash (that is, fine conversion) must be performed to provide the four lsbs. the 8-bit word is then placed on the data output bus. figure 6 and figure 7 show simplified schematics of the adc. when the adc starts a conversion, the track-and-hold goes into hold mode and holds the analog input for 120 ns. this is the acquisition phase, as shown in figure 6 , when switch 2 is in position a. at the point when the track-and-hold returns to its track mode, this signal is sampled by the sampling capacitor, as switch 2 moves into position b. the first flash occurs at this instant and is then followed by the second flash. typically, the first flash is complete after 100 ns, that is, at 220 ns; and the end of the second flash and, hence, the 8-bit conversion result is available at 330 ns (minimum). the maximum conversion time is 420 ns. as shown in figure 8 , the track-and-hold returns to track mode after 120 ns and starts the next acquisition before the end of the current conversion. figure 10 shows the adc transfer function. timing and control logic r1 hold sampling capacitor a b sw2 r16 r15 r14 r13 t/h 1 v in db7 db6 db5 db4 db3 db2 db1 db0 decode logic 14 15 13 1 output register output drivers reference 01321-006 figure 6. adc acquisition phase timing and control logic r1 hold sampling capacitor a b sw2 r16 r15 r14 r13 t/h 1 v in db7 db6 db5 db4 db3 db2 db1 db0 decode logic 14 15 13 1 output register output drivers reference 01321-007 figure 7. adc conversion phase hold hold 120ns convst eoc cs rd db0 to db7 t 2 track track valid data t 1 t 3 01321-008 figure 8. track-and-hold timing typical connection diagram figure 9 shows a typical connection diagram for the ad7822/ ad7825/ad7829. the agnd and dgnd are connected together at the device for good noise suppression. the parallel interface is implemented using an 8-bit data bus. the end of conversion signal ( eoc ) idles high, the falling edge of convst initiates a conversion, and at the end of conversion the falling edge of eoc is used to initiate an interrupt service routine (isr) on a microprocessor (see the parallel interface section for more details.) v ref and v mid are connected to a voltage source such as the ad780, and v dd is connected to a voltage source that can vary from 4.5 v to 5.5 v (see tabl e 5 in the analog input section). when v dd is first connected, the ad7822/ad7825/ ad7829 power up in a low current mode, that is, power-down mode, with the default logic level on the eoc pin on the ad7822 and ad7825 equal to a low. ensure the convst line is not floating when v dd is applied, because this can put the ad7822/ad7825/ad7829 into an unknown state.
ad7822/ad7825/ad7829 rev. c | page 11 of 28 a suggestion is to tie convst to v dd or dgnd through a pull-up or pull-down resistor. a rising edge on the convst pin causes the ad7829 to fully power up, while a rising edge on the pd pin causes the ad7822 and ad7825 to fully power up. for applica- tions where power consumption is of concern, the automatic power-down at the end of a conversion should be used to improve power performance (see the power vs. throughput section). supply 4 .5v to 5.5 v 10f 0.1f v dd v ref v mid v in1 1.25v to 3.75v input v in2 4 v in4 (v in8 5 ) agnd db0 to db7 eoc rd cs convst a0 1 a1 1 a2 2 pd 3 parallel interface c/p ad7822/ ad7825/ ad7829 dgnd 2.5v ad780 01321-009 1 a0, a1 ad7825/ad7829 2 a2 ad7829 3 pd ad7822/ad7825 4 v in2 to v in4 ad7825/ad7829 5 v in5 to v in8 ad7829 figure 9. typical connection diagram adc transfer function the output coding of the ad7822/ad7825/ad7829 is straight binary. the designed code transitions occur at successive integer lsb values (that is, 1 lsb, 2 lsbs, and so on). the lsb size = v ref /256 (v dd = 5 v) or the lsb size = (0.8 v ref )/256 (v dd = 3 v). the ideal transfer characteristic for the ad7822/ad7825/ ad7829 is shown in figure 10 . 11111111 111...110 111...000 10000000 000...111 000...010 00000000 (v dd = 5v) 1lsb = v ref /256 (v dd = 3v) 1lsb = 0.8v ref /256 000...001 adc code 1lsb v mid (v dd = 5v) v mid ? 1.25v (v dd = 3v) v mid ? 1v v mid + 1.25v ? 1lsb v mid + 1v ? 1lsb analog input voltage 0 1321-010 figure 10. transfer characteristic analog input the ad7822 has a single input channel, and the ad7825 and ad7829 have four and eight input channels, respectively. each input channel has an input span of 2.5 v or 2.0 v, depending on the supply voltage (v dd ). this input span is automatically set up by an on-chip v dd detector circuit. a 5 v operation of the adcs is detected when v dd exceeds 4.1 v, and a 3 v operation is detected when v dd falls below 3.8 v. this circuit also possesses a degree of glitch rejection; for example, a glitch from 5.5 v to 2.7 v up to 60 ns wide does not trip the v dd detector. the v mid pin is used to center this input span anywhere in the range of agnd to v dd . if no input voltage is applied to v mid , the default input range is agnd to 2.0 v (v dd = 3 v 10%), that is, centered about 1.0 v; or agnd to 2.5 v (v d d = 5 v 10%), that is, centered about 1.25 v. when using the default input range, the v mid pin can be left unconnected, or in some cases, it can be decoupled to agnd with a 0.1 f capacitor. if, however, an external v mid is applied, the analog input range is from v mid ? 1.0 v to v mid + 1.0 v (v dd = 3 v 10%), or from v mid ? 1.25 v to v mid + 1.25 v (v dd = 5 v 10%). the range of values of v mid that can be applied depends on the value of v dd . for v dd = 3 v 10%, the range of values that can be applied to v mid is from 1.0 v to v dd ? 1.0 v and from 1.25 v to v dd ? 1.25 v when v dd = 5 v 10%. table 5 shows the relevant ranges of v mid and the input span for various values of v dd . figure 11 illustrates the input signal range available with various values of v mid . table 5. v dd v mid internal v mid ext max v in span v mid ext min v in span unit 5.5 1.25 4.25 3.0 to 5.5 1.25 0 to 2.5 v 5.0 1.25 3.75 2.5 to 5.0 1.25 0 to 2.5 v 4.5 1.25 3.25 2.0 to 4.5 1.25 0 to 2.5 v 3.3 1.00 2.3 1.3 to 3.3 1.00 0 to 2.0 v 3.0 1.00 2.0 1.0 to 3.0 1.00 0 to 2.0 v 2.7 1.00 1.7 0.7 to 2.7 1.00 0 to 2.0 v
ad7822/ad7825/ad7829 rev. c | page 12 of 28 5v 4v 3v 2v 1v v dd = 5v input signal range for various v mid v mid = n/c (1.25v) v mid = 2.5v v mid = 3.75v 3v 2v 1v v dd = 3v input signal range for various v mid v mid = n/c (1v) v mid = 1.5v v mid = 2v 0 1321-011 figure 11. analog input span variation with v mid v mid can be used to remove offsets in a system by applying the offset to the v mid pin as shown in figure 12 , or it can be used to accommodate bipolar signals by applying v mid to a level-shifting circuit before v in , as shown in figure 13 . when v mid is being driven by an external source, the source can be directly tied to the level-shifting circuitry (see figure 13 ). however, if the internal v mid , that is, the default value, is being used as an output, it must be buffered before applying it to the level- shifting circuitry because the v mid pin has an impedance of approximately 6 k (see figure 14 ). v in v mid ad7822/ ad7825/ ad7829 v mid v in v mid 01321-012 figure 12. removing offsets using v mid v ref v mid v in r3 r4 r2 r1 v v 0v v in 0v 2.5v ad7822/ ad7825/ ad7829 2.5v 01321-013 figure 13. accommodating bipolar signals using external v mid r2 v ref v mid v in external 2.5v r3 r4 r1 v v 0 v v in 0v v mid ad7822/ ad7825/ ad7829 01321-014 figure 14. accommodating bipolar signals using internal v mid note: although there is a v ref pin from which a voltage reference of 2.5 v can be sourced, or to which an external reference can be applied, this does not provide an option of varying the value of the voltage reference. as stated in the specifications for the ad7822/ad7825/ad7829, the input voltage range at this pin is 2.5 v 2%. analog input structure figure 15 shows an equivalent circuit of the analog input structure of the ad7822/ad7825/ad7829. the two diodes, d1 and d2, provide esd protection for the analog inputs. care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 200 mv. doing so causes these diodes to become forward biased and start conducting current into the substrate. a maximum current of 20 ma can be conducted by these diodes without causing irreversible damage to the part. however, it is worth noting that a small amount of current (1 ma) being conducted into the substrate, due to an overvoltage on an unselected channel, can cause inaccurate conversions on a selected channel.
ad7822/ad7825/ad7829 rev. c | page 13 of 28 capacitor c2 in figure 15 is typically about 4 pf and can be primarily attributed to pin capacitance. the resistor, r1, is a lumped component made up of the on resistance of several components, including that of the multiplexer and the track- and-hold. this resistor is typically about 310 . capacitor c1 is the track-and-hold capacitor and has a capacitance of 0.5 pf. switch 1 is the track-and-hold switch, and switch 2 is that of the sampling capacitor, as shown in figure 6 and figure 7 . v in c2 4pf d1 d2 r1 310 ? sw1 c1 0.5pf a b sw2 v dd 01321-015 figure 15. equivalent analog input circuit when in track phase, switch 1 is closed and switch 2 is in position a. when in hold mode, switch 1 opens and switch 2 remains in position a. the track-and-hold remains in hold mode for 120 ns (see the circuit description section), after which it returns to track mode and the adc enters its conversion phase. at this point, switch 1 opens and switch 2 moves to position b. at the end of the conversion, switch 2 moves back to position a. analog input selection on power-up, the default v in selection is v in1 . when returning to normal operation from power-down, the v in selected is the same one that was selected prior to initiation of power-down. table 6 shows the multiplexer address corresponding to each analog input from v in1 to v in4(8) for the ad7825 or ad7829. table 6. a2 a1 a0 analog input selected 0 0 0 v in1 0 0 1 v in2 0 1 0 v in3 0 1 1 v in4 1 0 0 v in5 1 0 1 v in6 1 1 0 v in7 1 1 1 v in8 channel selection on the ad7825 and ad7829 is made without the necessity of a write operation. the address of the next channel to be converted is latched at the start of the current read operation, that is, on the falling edge of rd while cs is low, as shown in figure 16 . this allows for improved throughput rates in channel hopping applications. convst db0 to db7 a0 to a2 eoc cs rd t 2 t 1 t 3 t 13 valid data address channel y track chx track chx hold chx track chy hold chy 120ns 01321-016 figure 16. channel hopping timing there is a minimum time delay between the falling edge of rd and the next falling edge of the convst signal, t 13 . this is the minimum acquisition time required of the track-and-hold to maintain 8-bit performance. figure 17 shows the typical perform- ance of the ad7825 when channel hopping for various acquisition times. these results are obtained using an external reference and internal v mid while channel hopping between v in1 and v in4 with 0 v on channel 4 and 0.5 v on channel 1. acquisition time (ns) 8.0 5.0 10 500 200 enob 100 50 40 30 20 15 7.5 7.0 6.5 6.0 5.5 8.5 01321-017 figure 17. effective number of bits vs. acquisition time for the ad7825 the on-chip track-and-hold can accommodate input frequencies to 10 mhz, making the ad7822/ad7825/ad7829 ideal for subsampling applications. when the ad7825 is converting a 10 mhz input signal at a sampling rate of 2 msps, the effective number of bits typically remains above seven, corresponding to a signal-to-noise ratio of 42 dbs, as shown in figure 18 .
ad7822/ad7825/ad7829 rev. c | page 14 of 28 input frequency (mhz) 50 38 01 2. 01 snr (db) 34568 48 46 44 42 40 f sample = 2mhz 01321-018 figure 18. snr vs. input frequency on the ad7825 power-up times the ad7822/ad7825/ad7829 have a 1 s power-up time when using an external reference and a 25 s power-up time when using the on-chip reference. when v dd is first connected, the ad7822/ad7825/ad7829 are in a low current mode of operation. ensure that the convst line is not floating when v dd is applied. if there is a glitch on convst while v dd is rising, the part attempts to power up before v dd has fully settled and can enter an unknown state. to carry out a conversion, the ad7822/ad7825/ad7829 must first be powered up. the ad7829 is powered up by a rising edge on the convst pin, and a conversion is initiated on the falling edge of convst . figure 19 shows how to power up the ad7829 when v dd is first connected or after the ad7829 has been powered down using the convst pin when using either the on-chip reference or an external reference. when using an external reference, the falling edge of convst may occur before the required power-up time has elapsed; however, the conversion is not initiated on the falling edge of convst but rather at the moment when the part has completely powered up, that is, after 1 s. if the falling edge of convst occurs after the required power-up time has elapsed, then it is upon this falling edge that a conversion is initiated. when using the on-chip reference, it is necessary to wait the required power-up time of approximately 25 s before initiating a conversion; that is, a falling edge on convst must not occur before the required power-up time has elapsed, when v dd is first connected or after the ad7829 has been powered down using the convst pin, as shown in figure 19 . v dd t power-up 1s convst v dd convst t power-up 25s conversion initiated here conversion initiated here external reference on-chip reference 01321-019 figure 19. ad7829 power-up time figure 20 shows how to power up the ad7822 or ad7825 when v dd is first connected or after the adcs have been powered down, using the pd pin or the convst pin, with either the on-chip reference or an external reference. when the supplies are first connected or after the part has been powered down by the pd pin, only a rising edge on the pd pin causes the part to power up. when the part has been powered down using the convst pin, a rising edge on either the pd pin or the convst pin powers the part up again. as with the ad7829, when using an external reference with the ad7822 or ad7825, the falling edge of convst may occur before the required power-up time has elapsed. if this is the case, the conversion is not initiated on the falling edge of convst , but rather at the moment when the part has powered up completely, that is, after 1 s. if the falling edge of convst occurs after the required power-up time has elapsed, it is upon this falling edge that a conversion is initiated. when using the on-chip reference, it is necessary to wait the required power-up time of approximately 25 s before initiating a conversion; that is, a falling edge on convst must not occur before the required power-up time has elapsed, when supplies are first connected to the ad7822 or ad7825, or when the adcs have been powered down using the pd pin or the convst pin, as shown in figure 20 .
ad7822/ad7825/ad7829 rev. c | page 15 of 28 v dd pd convst t power-up 1s t power-up 1s conversion initiated here conversion initiated here external reference conversion initiated here conversion initiated here v dd pd convst t power-up t power-up on-chip reference 25s 25s 0 1321-020 figure 20. ad7822/ad7825 power-up time power vs. throughput superior power performance can be achieved by using the automatic power-down (mode 2) at the end of a conversion (see the operating modes section). figure 21 shows how the automatic power-down is implemented using the convst signal to achieve the optimum power performance for the ad7822/ad7825/ad7829. the duration of the convst pulse is set to be equal to or less than the power-up time of the devices (see the operating modes section). as the throughput rate is reduced, the device remains in its power- down state longer and the average power consumption over time drops accordingly. t power-up 1s 330ns t convert power-down t cycle 10s @ 100ksps convst 0 1321-022 figure 21. automatic power-down for example, if the ad7822 is operated in a continuous sampling mode, with a throughput rate of 100 ksps and using an external reference, the power consumption is calculated as follows. the power dissipation during normal operation is 36 mw, v dd = 3 v. if the power-up time is 1 s and the conversion time is 330 ns (@ +25c), the ad7822 can be said to dissipate 36 mw (maximum) for 1.33 s during each conversion cycle. if the throughput rate is 100 ksps, the cycle time is 10 s and the average power dissipated during each cycle is (1.33/10) (36 mw) = 4.79 mw. this calculation uses the minimum conversion time, thus giving the best-case power dissipation at this throughput rate. however, the actual power dissipated during each conversion cycle could increase, depending on the actual conversion time (up to a maximum of 420 ns). figure 22 shows the power vs. throughput rate for automatic full power-down. throughput (ksps) 100 10 0 005 0100 power (mw) 1 200 300 400 0.1 50 150 250 350 450 01321-023 figure 22. ad7822/ad7825/ad7829 power vs. throughput frequency (khz) 0 ?10 ?80 (db) ?40 ?50 ?60 ?70 ?20 ?30 0 113 142 170 198 227 255 283 312 340 368 396 425 453 481 510 538 566 595 623 651 680 708 736 765 793 821 850 878 906 935 963 28 57 85 991 2048 point fft sampling 2msps f in = 200khz 01321-024 figure 23. ad7822/ad7825/ad7829 snr operating modes the ad7822/ad7825/ad7829 have two possible modes of operation, depending on the state of the convst pulse approximately 100 ns after the end of a conversion, that is, upon the rising edge of the eoc pulse. mode 1 operation (high speed sampling) when the ad7822/ad7825/ad7829 are operated in mode 1, they are not powered down between conversions. this mode of operation allows high throughput rates to be achieved. figure 24 shows how this optimum throughput rate is achieved by bringing convst high before the end of a conversion, that is, before the eoc pulses low. when operating in this mode, a new conversion should not be initiated until 30 ns after the end of a read operation. this allows the track-and-hold to acquire the analog signal to 0.5 lsb accuracy.
ad7822/ad7825/ad7829 rev. c | page 16 of 28 mode 2 operation (aut omatic power-down) when the ad7822/ad7825/ad7829 are operated in mode 2 (see figure 25 ), they automatically power down at the end of a conversion. the convst signal is brought low to initiate a conversion and is left logic low until after the eoc goes high, that is, approximately 100 ns after the end of the conversion. the state of the convst signal is sampled at this point (that is, 530 ns maximum after convst falling edge), and the ad7822/ ad7825/ad7829 power down as long as convst is low. the adc is powered up again on the rising edge of the convst signal. superior power performance can be achieved in this mode of operation by powering up the ad7822/ad7825/ ad7829 only to carry out a conversion. the parallel interface of the ad7822/ad7825/ad7829 remains fully operational while the adcs are powered down. a read may occur while the part is powered down, and, therefore, it does not necessarily need to be placed within the eoc pulse, as shown in figure 25 . t 2 t 1 t 3 valid data convst eoc cs rd db0 to db7 track hold track hold 120ns 01321-025 figure 24. mode 1 operation convst eoc cs rd db0 to db7 t power-up t 1 valid data power down here 01321-026 figure 25. mode 2 operation
ad7822/ad7825/ad7829 rev. c | page 17 of 28 parallel interface the parallel interface of the ad7822/ad7825/ad7829 is eight bits wide. figure 26 shows a timing diagram illustrating the operational sequence of the ad7822/ad7825/ad7829 parallel interface. the multiplexer address is latched into the ad7822/ ad7825/ad7829 on the falling edge of the rd input. the on- chip track-and-hold goes into hold mode on the falling edge of convst , and a conversion is also initiated at this point. when the conversion is complete, the end of conversion line ( eoc ) pulses low to indicate that new data is available in the output register of the ad7822/ad7825/ad7829. the eoc pulse stays logic low for a maximum time of 110 ns. however, the eoc pulse can be reset high by a rising edge of rd . this eoc line can be used to drive an edge-triggered interrupt of a microprocessor. cs and rd going low accesses the 8-bit conversion result. it is possible to tie cs permanently low and use only rd to access the data. in systems where the part is interfaced to a gate array or asic, this eoc pulse can be applied to the cs and rd inputs to latch data out of the ad7822/ ad7825/ad7829 and into the gate array or asic. this means that the gate array or asic does not need any conversion status recognition logic, and it also eliminates the logic required in the gate array or asic to generate the read signal for the ad7822/ ad7825/ad7829. convst eoc cs rd db0 to db7 a0 to a2 t 1 t 4 t 5 t 6 t 7 t 8 t 3 t 9 t 10 t 11 t 12 t 13 valid data next channel address t 2 01321-027 figure 26. ad7822/ad7825/ad7829 parallel port timing
ad7822/ad7825/ad7829 rev. c | page 18 of 28 microprocessor interfacing the parallel port on the ad7822/ad7825/ad7829 allows the adcs to be interfaced to a range of many different micro- controllers. this section explains how to interface the ad7822/ ad7825/ad7829 with some of the more common microcontroller parallel interface protocols. ad7822/ad7825/ad7829 to 8051 figure 27 shows a parallel interface between the ad7822/ad7825/ ad7829 and the 8051 microcontroller. the eoc signal on the ad7822/ad7825/ad7829 provides an interrupt request to the 8051 when a conversion ends and data is ready. port 0 of the 8051 can serve as an input or output port; or, as in this case when used together with the address latch enable (ale) of the 8051, can be used as a bidirectional low order address and data bus. the ale output of the 8051 is used to latch the low byte of the address during accesses to the device, while the high order address byte is supplied from port 2. port 2 latches remain stable when the ad7822/ad7825/ ad7829 are addressed because they do not have to be turned around (set to 1) for data input, as is the case for port 0. ad0 to ad7 ale a8 to a15 rd int 8051 1 latch decoder db0 to db7 rd eoc cs 1 additional pins omitted for clarity. ad7822/ ad7825/ ad7829 1 01321-028 figure 27. interfacing to the 8051 ad7822/ad7825/ad7829 to pic16c6x/pic16c7x figure 28 shows a parallel interface between the ad7822/ ad7825/ad7829 and the pic16c64/pic16c65/pic16c74. the eoc signal on the ad7822/ad7825/ad7829 provides an interrupt request to the microcontroller when a conversion begins. of the pic16c6x/pic16c7x range of microcontrollers, only the pic16c64/pic16c65/pic16c74 can provide the option of a parallel slave port. port d of the microcontroller operates as an 8-bit wide parallel slave port when control bit pspmode in the trise register is set. setting pspmode enables port pin re0 to be the rd output and re2 to be the cs (chip select) output. for this functionality, the corresponding data direction bits of the trise register must be configured as outputs (reset to 0). see the pic16c6x/pic16c7x microcontroller user manual. psp0 to psp7 rd int pic16c6x/7x 1 db0 to db7 rd eoc cs 1 additional pins omitted for clarity. cs ad7822/ ad7825/ ad7829 1 01321-029 figure 28. interfacing to the pic16c6x/ pic16c7x ad7822/ad7825/ad7829 to adsp-21xx figure 29 shows a parallel interface between the ad7822/ ad7825/ad7829 and the adsp-21xx series of dsps. as before, the eoc signal on the ad7822/ad7825/ad7829 provides an interrupt request to the dsp when a conversion ends. d7 to d0 rd irq adsp-21xx 1 db0 to db7 rd eoc cs 1 additional pins omitted for clarity. dms en address decode logic a13 to a0 ad7822/ ad7825/ ad7829 1 01321-030 figure 29. interfacing to the adsp-21xx interfacing multiplexer address inputs figure 30 shows a simplified interfacing scheme between the ad7825/ad7829 and any microprocessor or microcontroller, which facilitates easy channel selection on the adcs. the multi- plexer address is latched on the falling edge of the rd signal, as outlined in the parallel interface section, allowing the use of the three lsbs of the address bus to select the channel address. as shown in figure 30 , only address bit a3 to address bit a15 are address decoded, allowing a0 to a2 to be changed according to desired channel selection without affecting chip selection.
ad7822/ad7825/ad7829 rev. c | page 19 of 28 ad7822 standalone operation the ad7822, being the single channel device, does not have any multiplexer addressing associated with it and can be controlled with just one signal, that is, the convst signal. as shown in figure 31 , the rd and cs pins are both tied to the eoc pin. the resulting signal can be used as an interrupt request signal (irq) on a dsp, as a wr signal to memory, or as a clk to a latch or asic. the timing for this interface, as shown in figure 31 , demonstrates how, with the convst signal alone, a conversion can be initiated, data is latched out, and the operating mode of the ad7822 can be selected. ad7825/ ad7829 a0 a1 a2 cs rd db7 to db0 cs rd db0 to db7 a15 to a3 a2 to a0 adc i/o address mux address a/d result mux address (channel selection a0 to a2) latched microprocessor read cycle address decode system bus 01321-031 a15 to a3 figure 30. ad7825/ad7829 simplified microinterfacing scheme convst rd cs eoc db7 to db0 ad7822 dsp/ latch/asic convst eoc rd cs db0 to db7 a/d result t 1 t 4 01321-032 figure 31. ad7822 standalone operation
ad7822/ad7825/ad7829 rev. c | page 20 of 28 outline dimensions controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. corner leads may be configured as whole or half leads. compliant to jedec standards ms-001-ad 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 20 1 10 11 0.100 (2.54) bsc 1.060 (26.92) 1.030 (26.16) 0.980 (24.89) pin 1 0.210 (5.33) max seating plane 0.015 (0.38) min 0.005 (0.13) min 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.060 (1.52) max 0.430 (10.92) max 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.015 (0.38) gauge plane 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) figure 32. 20-lead plastic dual in-line package [pdip] narrow body (n-20) dimensions shown in inches and (millimeters) controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-013-ac 13.00 (0.5118) 12.60 (0.4961) 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 0 . 7 5 ( 0 . 0 2 9 5 ) 0 . 2 5 ( 0 . 0 0 9 8 ) 1.27 (0.0500) 0.40 (0.0157) coplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) seating plane 8 0 20 11 10 1 1.27 (0.0500) bsc 060706-a 45 figure 33. 20-lead standard small outline package [soic_w] wide body (rw-20) dimensions shown in millimeters and (inches)
ad7822/ad7825/ad7829 rev. c | page 21 of 28 compliant to jedec standards mo-153-ac 20 1 11 10 6.40 bsc 4.50 4.40 4.30 pin 1 6.60 6.50 6.40 seating plane 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 coplanarit y 0.10 figure 34. 20-lead thin shrink small outline package [tssop] (ru-20) dimensions shown in millimeters controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. corner leads may be configured as whole or half leads. compliant to jedec standards ms-001-af 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 24 1 12 13 0.100 (2.54) bsc 1.280 (32.51) 1.250 (31.75) 1.230 (31.24) pin 1 0.210 (5.33) max seating plane 0.015 (0.38) min 0.005 (0.13) min 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.060 (1.52) max 0.430 (10.92) max 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.015 (0.38) gauge plane 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) figure 35. 24-lead plastic dual in-line package [pdip] narrow body (n-24-1) dimensions shown in inches and (millimeters)
ad7822/ad7825/ad7829 rev. c | page 22 of 28 compliant to jedec standards ms-013-ad controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. 15.60 (0.6142) 15.20 (0.5984) 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 0 . 7 5 ( 0 . 0 2 9 5 ) 0 . 2 5 ( 0 . 0 0 9 8 ) 45 1.27 (0.0500) 0.40 (0.0157) coplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) seating plane 8 0 24 13 12 1 1.27 (0.0500) bsc 060706-a figure 36. 24-lead standard small outline package [soic_w] wide body (rw-24) dimensions shown in millimeters and (inches) 24 13 12 1 6.40 bsc 4.50 4.40 4.30 pin 1 7.90 7.80 7.70 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 seating plane 0.10 coplanarity compliant to jedec standards mo-153-ad figure 37. 24-lead thin shrink small outline package [tssop] (ru-24) dimensions shown in millimeters
ad7822/ad7825/ad7829 rev. c | page 23 of 28 controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. corner leads may be configured as whole or half leads. compliant to jedec standards ms-011-ab 0.100 (2.54) bsc 1.565 (39.75) 1.380 (35.05) pin 1 0.580 (14.73) 0.485 (12.31) 0.022 (0.56) 0.014 (0.36) 0.200 (5.08) 0.115 (2.92) 0.070 (1.78) 0.030 (0.76) 0.250 (6.35) max seating plane 0.015 (0.38) min 0.005 (0.13) min 0.700 (17.78) max 0.015 (0.38) 0.008 (0.20) 0.625 (15.88) 0.600 (15.24) 0.015 (0.38) gauge plane 0.195 (4.95) 0.125 (3.17) 28 11 4 15 figure 38. 28-lead plastic dual in-line package [pdip] wide body (n-28-2) dimensions shown in inches and (millimeters) controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-013-ae 18.10 (0.7126) 17.70 (0.6969) 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 0 . 7 5 ( 0 . 0 2 9 5 ) 0 . 2 5 ( 0 . 0 0 9 8 ) 45 1.27 (0.0500) 0.40 (0.0157) coplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) seating plane 8 0 28 15 14 1 1.27 (0.0500) bsc 060706-a figure 39. 28-lead standard small outline package [soic_w] wide body (rw-28) dimensions shown in millimeters and (inches)
ad7822/ad7825/ad7829 rev. c | page 24 of 28 compliant to jedec standards mo-153-ae 28 15 14 1 8 0 seating plane c oplanarit y 0.10 1.20 max 6.40 bsc 0.65 bsc pin 1 0.30 0.19 0.20 0.09 4.50 4.40 4.30 0.75 0.60 0.45 9.80 9.70 9.60 0.15 0.05 figure 40. 28-lead thin shrink small outline package [tssop] (ru-28) dimensions shown in millimeters
ad7822/ad7825/ad7829 rev. c | page 25 of 28 ordering guide model temperature range package descri ption package option linearity error ad7822bn ?40c to +85c 20-lead pdip n-20 0.75 lsb ad7822bnz 1 ?40c to +85c 20-lead pdip n-20 0.75 lsb ad7822br ?40c to +85c 20-lead soic_w rw-20 0.75 lsb ad7822br-reel ?40c to +85c 20-lead soic_w rw-20 0.75 lsb ad7822br-reel7 ?40c to +85c 20-lead soic_w rw-20 0.75 lsb ad7822brz 1 ?40c to +85c 20-lead soic_w rw-20 0.75 lsb ad7822brz-reel 1 ?40c to +85c 20-lead soic_w rw-20 0.75 lsb ad7822brz-reel7 1 ?40c to +85c 20-lead soic_w rw-20 0.75 lsb ad7822bru ?40c to +85c 20-lead tssop ru-20 0.75 lsb ad7822bru-reel ?40c to +85c 20-lead tssop ru-20 0.75 lsb ad7822bru-reel7 ?40c to +85c 20-lead tssop ru-20 0.75 lsb AD7822BRUZ 1 ?40c to +85c 20-lead tssop ru-20 0.75 lsb AD7822BRUZ-reel 1 ?40c to +85c 20-lead tssop ru-20 0.75 lsb AD7822BRUZ-reel7 1 ?40c to +85c 20-lead tssop ru-20 0.75 lsb ad7825bn ?40c to +85c 24-lead pdip n-24-1 0.75 lsb ad7825bnz 1 ?40c to +85c 24-lead pdip n-24-1 0.75 lsb ad7825br ?40c to +85c 24-lead soic_w rw-24 0.75 lsb ad7825br-reel ?40c to +85c 24-lead soic_w rw-24 0.75 lsb ad7825br-reel7 ?40c to +85c 24-lead soic_w rw-24 0.75 lsb ad7825brz 1 ?40c to +85c 24-lead soic_w rw-24 0.75 lsb ad7825brz-reel 1 ?40c to +85c 24-lead soic_w rw-24 0.75 lsb ad7825brz-reel7 1 ?40c to +85c 24-lead soic_w rw-24 0.75 lsb ad7825bru ?40c to +85c 24-lead tssop ru-24 0.75 lsb ad7825bru-reel ?40c to +85c 24-lead tssop ru-24 0.75 lsb ad7825bru-reel7 ?40c to +85c 24-lead tssop ru-24 0.75 lsb ad7825bruz 1 ?40c to +85c 24-lead tssop ru-24 0.75 lsb ad7825bruz-reel 1 ?40c to +85c 24-lead tssop ru-24 0.75 lsb ad7825bruz-reel7 1 ?40c to +85c 24-lead tssop ru-24 0.75 lsb ad7829bn ?40c to +85c 28-lead pdip n-28-2 0.75 lsb ad7829bnz 1 ?40c to +85c 28-lead pdip n-28-2 0.75 lsb ad7829br ?40c to +85c 28-lead soic_w rw-28 0.75 lsb ad7829br-reel ?40c to +85c 28-lead soic_w rw-28 0.75 lsb ad7829br-reel7 ?40c to +85c 28-lead soic_w rw-28 0.75 lsb ad7829brz 1 ?40c to +85c 28-lead soic_w rw-28 0.75 lsb ad7829brz-reel 1 ?40c to +85c 28-lead soic_w rw-28 0.75 lsb ad7829brz-reel7 1 ?40c to +85c 28-lead soic_w rw-28 0.75 lsb ad7829bru ?40c to +85c 28-lead tssop ru-28 0.75 lsb ad7829bru-reel ?40c to +85c 28-lead tssop ru-28 0.75 lsb ad7829bru-reel7 ?40c to +85c 28-lead tssop ru-28 0.75 lsb ad7829bruz 1 ?40c to +85c 28-lead tssop ru-28 0.75 lsb ad7829bruz-reel 1 ?40c to +85c 28-lead tssop ru-28 0.75 lsb ad7829bruz-reel7 1 ?40c to +85c 28-lead tssop ru-28 0.75 lsb 1 z = pb-free part.
ad7822/ad7825/ad7829 rev. c | page 26 of 28 notes
ad7822/ad7825/ad7829 rev. c | page 27 of 28 notes
ad7822/ad7825/ad7829 rev. c | page 28 of 28 notes ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. c01321-0-8/06(c)

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